Ilya A. Volynets-Evenbakh
IP27 patches
Some are borrowed from ths & Bacchus
Little piece is mine
Index: arch/mips/Makefile
===================================================================
RCS file: /home/cvs/linux/arch/mips/Makefile,v
retrieving revision 1.195
diff -u -r1.195 Makefile
--- arch/mips/Makefile 3 Jun 2005 13:08:04 -0000 1.195
+++ arch/mips/Makefile 4 Jul 2005 02:08:59 -0000
@@ -16,7 +16,7 @@
-xassembler /dev/null > /dev/null 2>&1; then echo "$(1)"; \
else echo "$(2)"; fi ;)
-cflags-y :=
+cflags-y := -ffreestanding
#
# Select the object file format to substitute into the linker script.
@@ -68,7 +68,7 @@
vmlinux-32 = vmlinux.32
vmlinux-64 = vmlinux
else
-gas-abi = 32
+gas-abi = o32
ld-emul = $(32bit-emul)
vmlinux-32 = vmlinux
vmlinux-64 = vmlinux.64
@@ -129,7 +129,7 @@
else \
gcc_abi=; gcc_isa=-$(5); \
fi; \
-gas_abi=-Wa,-$(gcc-abi); gas_cpu=$$cpu; gas_isa=-Wa,$$isa; \
+gas_abi=-Wa,-mabi=$(gcc-abi); gas_cpu=$$cpu; gas_isa=-Wa,$$isa; \
while :; do \
for gas_opt in -Wa,-march= -Wa,-mcpu=; do \
$(CC) $$gas_abi $$gas_opt$$cpu $$gas_isa -Wa,-Z -c \
@@ -140,7 +140,7 @@
break; \
done; \
if test "$(gcc-abi)" != "$(gas-abi)"; then \
- gas_abi="-Wa,-$(gas-abi) -Wa,-mgp$(gcc-abi)"; \
+ gas_abi="-Wa,-mabi=$(gas-abi) -Wa,-mgp$(gcc-abi)"; \
fi; \
if test "$$gcc_opt" = -march= && test -n "$$gcc_abi"; then \
$(CC) $$gcc_abi $$gcc_opt$$gcc_cpu -S -o /dev/null \
Index: arch/mips/mm/c-r4k.c
===================================================================
RCS file: /home/cvs/linux/arch/mips/mm/c-r4k.c,v
retrieving revision 1.108
diff -u -r1.108 c-r4k.c
--- arch/mips/mm/c-r4k.c 25 Apr 2005 16:36:23 -0000 1.108
+++ arch/mips/mm/c-r4k.c 4 Jul 2005 02:09:01 -0000
@@ -1213,6 +1213,12 @@
}
}
+/*
+ * This variable indicates if we prepared boot cpu caches yet or not.
+ * Secondary CPUs don't need to change any global data/memory
+ */
+static __initdata int boot_cpu_ready=0;
+
void __init ld_mmu_r4xx0(void)
{
extern void build_clear_page(void);
@@ -1222,51 +1228,55 @@
/* Default cache error handler for R4000 and R5000 family */
memcpy((void *)(CAC_BASE + 0x100), &except_vec2_generic, 0x80);
- memcpy((void *)(UNCAC_BASE + 0x100), &except_vec2_generic, 0x80);
-
+ /* This only needs to happen once. One above can be done locally to fill in the local cache? */
+ if(boot_cpu_ready==0){
+ memcpy((void *)(UNCAC_BASE + 0x100), &except_vec2_generic, 0x80);
+ }
probe_pcache();
setup_scache();
- r4k_blast_dcache_page_setup();
- r4k_blast_dcache_page_indexed_setup();
- r4k_blast_dcache_setup();
- r4k_blast_icache_page_setup();
- r4k_blast_icache_page_indexed_setup();
- r4k_blast_icache_setup();
- r4k_blast_scache_page_setup();
- r4k_blast_scache_page_indexed_setup();
- r4k_blast_scache_setup();
-
- /*
- * Some MIPS32 and MIPS64 processors have physically indexed caches.
- * This code supports virtually indexed processors and will be
- * unnecessarily inefficient on physically indexed processors.
- */
- shm_align_mask = max_t( unsigned long,
- c->dcache.sets * c->dcache.linesz - 1,
- PAGE_SIZE - 1);
-
- flush_cache_all = r4k_flush_cache_all;
- __flush_cache_all = r4k___flush_cache_all;
- flush_cache_mm = r4k_flush_cache_mm;
- flush_cache_page = r4k_flush_cache_page;
- flush_icache_page = r4k_flush_icache_page;
- flush_cache_range = r4k_flush_cache_range;
-
- flush_cache_sigtramp = r4k_flush_cache_sigtramp;
- flush_icache_all = r4k_flush_icache_all;
- flush_data_cache_page = r4k_flush_data_cache_page;
- flush_icache_range = r4k_flush_icache_range;
+ if(boot_cpu_ready==0) {
+ r4k_blast_dcache_page_setup();
+ r4k_blast_dcache_page_indexed_setup();
+ r4k_blast_dcache_setup();
+ r4k_blast_icache_page_setup();
+ r4k_blast_icache_page_indexed_setup();
+ r4k_blast_icache_setup();
+ r4k_blast_scache_page_setup();
+ r4k_blast_scache_page_indexed_setup();
+ r4k_blast_scache_setup();
+
+ /*
+ * Some MIPS32 and MIPS64 processors have physically indexed caches.
+ * This code supports virtually indexed processors and will be
+ * unnecessarily inefficient on physically indexed processors.
+ */
+ shm_align_mask = max_t( unsigned long,
+ c->dcache.sets * c->dcache.linesz - 1,
+ PAGE_SIZE - 1);
+
+ flush_cache_all = r4k_flush_cache_all;
+ __flush_cache_all = r4k___flush_cache_all;
+ flush_cache_mm = r4k_flush_cache_mm;
+ flush_cache_page = r4k_flush_cache_page;
+ flush_icache_page = r4k_flush_icache_page;
+ flush_cache_range = r4k_flush_cache_range;
+
+ flush_cache_sigtramp = r4k_flush_cache_sigtramp;
+ flush_icache_all = r4k_flush_icache_all;
+ flush_data_cache_page = r4k_flush_data_cache_page;
+ flush_icache_range = r4k_flush_icache_range;
#ifdef CONFIG_DMA_NONCOHERENT
- _dma_cache_wback_inv = r4k_dma_cache_wback_inv;
- _dma_cache_wback = r4k_dma_cache_wback_inv;
- _dma_cache_inv = r4k_dma_cache_inv;
+ _dma_cache_wback_inv = r4k_dma_cache_wback_inv;
+ _dma_cache_wback = r4k_dma_cache_wback_inv;
+ _dma_cache_inv = r4k_dma_cache_inv;
#endif
- __flush_cache_all();
+ build_clear_page();
+ build_copy_page();
+ boot_cpu_ready++;
+ }
+ local_r4k___flush_cache_all(NULL);
coherency_setup();
-
- build_clear_page();
- build_copy_page();
}
Index: arch/mips/mm/pg-r4k.c
===================================================================
RCS file: /home/cvs/linux/arch/mips/mm/pg-r4k.c,v
retrieving revision 1.16
diff -u -r1.16 pg-r4k.c
--- arch/mips/mm/pg-r4k.c 15 Jan 2005 01:31:05 -0000 1.16
+++ arch/mips/mm/pg-r4k.c 4 Jul 2005 02:09:01 -0000
@@ -404,9 +404,6 @@
build_jr_ra();
- flush_icache_range((unsigned long)&clear_page_array,
- (unsigned long) epc);
-
BUG_ON(epc > clear_page_array + ARRAY_SIZE(clear_page_array));
}
@@ -482,8 +479,5 @@
build_jr_ra();
- flush_icache_range((unsigned long)©_page_array,
- (unsigned long) epc);
-
BUG_ON(epc > copy_page_array + ARRAY_SIZE(copy_page_array));
}
Index: arch/mips/mm/tlbex.c
===================================================================
RCS file: /home/cvs/linux/arch/mips/mm/tlbex.c,v
retrieving revision 1.26
diff -u -r1.26 tlbex.c
--- arch/mips/mm/tlbex.c 30 Jun 2005 10:51:01 -0000 1.26
+++ arch/mips/mm/tlbex.c 4 Jul 2005 02:09:03 -0000
@@ -743,7 +743,6 @@
#endif
memcpy((void *)CAC_BASE, tlb_handler, 0x80);
- flush_icache_range(CAC_BASE, CAC_BASE + 0x80);
}
/*
@@ -1256,7 +1255,6 @@
#endif
memcpy((void *)CAC_BASE, final_handler, 0x100);
- flush_icache_range(CAC_BASE, CAC_BASE + 0x100);
}
/*
@@ -1517,9 +1515,6 @@
printk("%08x\n", handle_tlbl[i]);
}
#endif
-
- flush_icache_range((unsigned long)handle_tlbl,
- (unsigned long)handle_tlbl + FASTPATH_SIZE * sizeof(u32));
}
static void __init build_r3000_tlb_store_handler(void)
@@ -1557,9 +1552,6 @@
printk("%08x\n", handle_tlbs[i]);
}
#endif
-
- flush_icache_range((unsigned long)handle_tlbs,
- (unsigned long)handle_tlbs + FASTPATH_SIZE * sizeof(u32));
}
static void __init build_r3000_tlb_modify_handler(void)
@@ -1597,9 +1589,6 @@
printk("%08x\n", handle_tlbm[i]);
}
#endif
-
- flush_icache_range((unsigned long)handle_tlbm,
- (unsigned long)handle_tlbm + FASTPATH_SIZE * sizeof(u32));
}
/*
@@ -1689,9 +1678,6 @@
printk("%08x\n", handle_tlbl[i]);
}
#endif
-
- flush_icache_range((unsigned long)handle_tlbl,
- (unsigned long)handle_tlbl + FASTPATH_SIZE * sizeof(u32));
}
static void __init build_r4000_tlb_store_handler(void)
@@ -1728,9 +1714,6 @@
printk("%08x\n", handle_tlbs[i]);
}
#endif
-
- flush_icache_range((unsigned long)handle_tlbs,
- (unsigned long)handle_tlbs + FASTPATH_SIZE * sizeof(u32));
}
static void __init build_r4000_tlb_modify_handler(void)
@@ -1768,9 +1751,6 @@
printk("%08x\n", handle_tlbm[i]);
}
#endif
-
- flush_icache_range((unsigned long)handle_tlbm,
- (unsigned long)handle_tlbm + FASTPATH_SIZE * sizeof(u32));
}
void __init build_tlb_refill_handler(void)
Index: arch/mips/pci/pci.c
===================================================================
RCS file: /home/cvs/linux/arch/mips/pci/pci.c,v
retrieving revision 1.30
diff -u -r1.30 pci.c
--- arch/mips/pci/pci.c 16 Dec 2004 12:55:01 -0000 1.30
+++ arch/mips/pci/pci.c 4 Jul 2005 02:09:04 -0000
@@ -20,11 +20,11 @@
* Make this long-lived so that we know when shutting down
* whether we probed only or not.
*/
-int pci_probe_only;
+int pci_probe_only = 1;
#define PCI_ASSIGN_ALL_BUSSES 1
-unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES;
+unsigned int pci_probe = 0; // PCI_ASSIGN_ALL_BUSSES;
/*
* The PCI controller list.
Index: include/asm-mips/atomic.h
===================================================================
RCS file: /home/cvs/linux/include/asm-mips/atomic.h,v
retrieving revision 1.40
diff -u -r1.40 atomic.h
--- include/asm-mips/atomic.h 23 Jun 2005 15:57:18 -0000 1.40
+++ include/asm-mips/atomic.h 4 Jul 2005 02:09:19 -0000
@@ -68,8 +68,8 @@
" sc %0, %1 \n"
" beqzl %0, 1b \n"
" .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
+ : "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} else if (cpu_has_llsc) {
unsigned long temp;
@@ -80,8 +80,8 @@
" sc %0, %1 \n"
" beqz %0, 1b \n"
" .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
+ : "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} else {
unsigned long flags;
@@ -110,8 +110,8 @@
" sc %0, %1 \n"
" beqzl %0, 1b \n"
" .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
+ : "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} else if (cpu_has_llsc) {
unsigned long temp;
@@ -122,8 +122,8 @@
" sc %0, %1 \n"
" beqz %0, 1b \n"
" .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
+ : "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} else {
unsigned long flags;
@@ -152,9 +152,8 @@
" addu %0, %1, %3 \n"
" sync \n"
" .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
+ : "=&r" (result), "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} else if (cpu_has_llsc) {
unsigned long temp;
@@ -167,9 +166,8 @@
" addu %0, %1, %3 \n"
" sync \n"
" .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
+ : "=&r" (result), "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} else {
unsigned long flags;
@@ -199,9 +197,8 @@
" subu %0, %1, %3 \n"
" sync \n"
" .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
+ : "=&r" (result), "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} else if (cpu_has_llsc) {
unsigned long temp;
@@ -214,9 +211,8 @@
" subu %0, %1, %3 \n"
" sync \n"
" .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
+ : "=&r" (result), "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} else {
unsigned long flags;
@@ -254,9 +250,8 @@
" sync \n"
"1: \n"
" .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
+ : "=&r" (result), "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} else if (cpu_has_llsc) {
unsigned long temp;
@@ -270,9 +265,8 @@
" sync \n"
"1: \n"
" .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
+ : "=&r" (result), "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} else {
unsigned long flags;
@@ -393,8 +387,8 @@
" scd %0, %1 \n"
" beqzl %0, 1b \n"
" .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
+ : "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} else if (cpu_has_llsc) {
unsigned long temp;
@@ -405,8 +399,8 @@
" scd %0, %1 \n"
" beqz %0, 1b \n"
" .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
+ : "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} else {
unsigned long flags;
@@ -435,8 +429,8 @@
" scd %0, %1 \n"
" beqzl %0, 1b \n"
" .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
+ : "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} else if (cpu_has_llsc) {
unsigned long temp;
@@ -447,8 +441,8 @@
" scd %0, %1 \n"
" beqz %0, 1b \n"
" .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
+ : "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} else {
unsigned long flags;
@@ -477,9 +471,8 @@
" addu %0, %1, %3 \n"
" sync \n"
" .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
+ : "=&r" (result), "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} else if (cpu_has_llsc) {
unsigned long temp;
@@ -492,9 +485,8 @@
" addu %0, %1, %3 \n"
" sync \n"
" .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
+ : "=&r" (result), "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} else {
unsigned long flags;
@@ -524,9 +516,8 @@
" subu %0, %1, %3 \n"
" sync \n"
" .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
+ : "=&r" (result), "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} else if (cpu_has_llsc) {
unsigned long temp;
@@ -539,9 +530,8 @@
" subu %0, %1, %3 \n"
" sync \n"
" .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
+ : "=&r" (result), "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} else {
unsigned long flags;
@@ -579,9 +569,8 @@
" sync \n"
"1: \n"
" .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
+ : "=&r" (result), "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} else if (cpu_has_llsc) {
unsigned long temp;
@@ -595,9 +584,8 @@
" sync \n"
"1: \n"
" .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
+ : "=&r" (result), "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} else {
unsigned long flags;